Apparatus for detecting pattern alignment error

ABSTRACT

An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied of the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern for detecting an alignment error in response to a position of the conductive via. The apparatus for detecting pattern alignment error can detect the alignment of lower wiring in a device with multi-layer wiring.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 10-2007-91798 filed on Sep. 10, 2007, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to an apparatus for detecting a patternalignment error.

Recent, developments in semiconductor device fabrication have led to atechnology for fabricating a semiconductor package with a semiconductordevice and a circuit board on which the semiconductor package ismounted.

In the development, the semiconductor device, semiconductor package andcircuit board may have a multi-layered wiring structure.

For example, a circuit board may include wirings disposed on differentlayers in order to input or output various types of signals.

In this technology, in order to form the wirings in different layers, alower wiring is formed on a lower insulation member, and the lowerwiring is insulated by an upper insulation member. Subsequently, anupper wiring is formed on the upper insulation member, and the upperwiring is then electrically connected to the lower wiring through aconductive via.

However, when the wirings are disposed on different layers, they areoften not aligned accurately, and the upper wiring and lower wiring endup not being connected to each other through the conductive via.

An alignment error of the upper wiring can be easily recognized througha visual test while, but an alignment error of the lower wiring is hardto recognized through a visual test because the lower wiring has beencovered by the upper insulation member.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to an apparatus fordetecting pattern alignment error, and more specifically to an apparatusthat is adapted to detect the alignment of the lower wiring of a devicewith multi-layered wiring.

In one embodiment, an apparatus for detecting pattern alignment errormay comprise a first conductive pattern disposed over a first insulationmember with a power source applied to the first conductive pattern; asecond insulation member covering the first conductive pattern; a secondconductive pattern disposed on the second insulation layer; a conductivevia connected to the second conductive pattern and passing through thesecond insulation member; and an insulation pattern disposed in thefirst conductive pattern for detecting an alignment error in response toa position of the conductive via.

The insulation pattern may be a through hole passing through the firstconductive pattern. Alternatively, the insulation pattern may bedisposed over the first conductive pattern.

The power source is a DC voltage. An area of the insulation pattern isabout 105 to 200% of the area of the conductive via. The insulationpattern may have a circular shape when viewed from above with a diameterof 50 μm to 200 μm.

The apparatus for detecting pattern alignment error may further comprisea third conductive pattern disposed over the second insulation memberand an additional conductive via passing through the second insulationmember that connects the third conductive pattern to the firstconductive pattern; and a power line that is electrically connected tothe third conductive pattern rather than the first conductive patternand a power source applied to the power line.

A plated layer may be formed on the second and third conductive patternsin a case where the conductive via is disposed over the first conductivepattern.

The plated layer will be formed only on the third conductive pattern ina case where the conductive via is disposed over the insulation patternrather than the first conductive pattern.

The apparatus for detecting a pattern alignment error may include anumber of second conductive patterns and insulation patternscorresponding to each second conductive pattern, and the insulationpatterns may all be different sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a first embodiment of the presentinvention.

FIG. 2 is a cross-sectional view taken along line I-I′ in FIG. 1.

FIG. 3 is a cross-sectional view illustrating that a first conductivepattern shown in FIG. 2 is disposed out of the alignment error range.

FIG. 4 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a second embodiment of the presentinvention.

FIG. 5 is a cross-sectional view taken along line II-II′ in FIG. 4.

FIG. 6 is a cross-sectional view illustrating that a first conductivepattern shown in FIG. 5 is disposed out of the alignment error range.

FIG. 7 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a third embodiment of the presentinvention.

FIG. 8 is a cross-sectional view taken along line III-III′ in FIG. 7.

FIG. 9 is a cross-sectional view illustrating that a first conductivepattern shown in FIG. 8 is disposed out of the alignment error range.

FIG. 10 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a fourth embodiment of the presentinvention.

FIG. 11 is a cross-sectional view taken along line IV-IV′ in FIG. 9.

FIG. 12 is a cross-sectional view illustrating that a first conductivepattern shown in FIG. 11 is disposed out of the alignment error range.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereafter, an apparatus for detecting a pattern alignment error inaccordance with embodiments of the present invention will be describedwith reference to the attached drawings.

The apparatus for detecting a pattern alignment error to be describedherein after is disposed at a periphery of an active area on which amulti-layered wiring is formed. Also, a first conductive pattern of theapparatus for detecting a pattern alignment error is formedsimultaneously with the lower wiring disposed at the active area. Asecond pattern is formed simultaneously with the upper wiring disposedat the active area.

FIG. 1 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a first embodiment of the presentinvention. FIG. 2 is a cross-sectional view taken along line I-I′ inFIG. 1 showing a case where the first conductive layer is formed withinthe alignment error range. FIG. 3 shows a case where the firstconductive layer is formed outside of the alignment error range.

Referring to FIGS. 1, 2, and 3, the pattern alignment error detectingapparatus 100 includes a first insulation member 110, a first conductivepattern 120 having an insulation pattern 125, a second insulation member130, and a second conductive pattern 150 having a conductive via 145.

The first conductive pattern 120 is disposed over the first insulationmember 110 which includes insulation material. The first conductivepattern 120 may be electrically connected, for example, to a power line(not shown) through which a DC power source Vd is applied.

In the present embodiment, an example of material which may be used asthe first conductive pattern 120 and the power line include aluminum,aluminum alloy, copper, cooper alloy, metal alloy, etc.

The first conductive pattern 120 includes the insulation pattern 125.The insulation pattern 125 may be disposed, for example, in the centerpart of the first conductive pattern 120. In the present embodiment, theinsulation pattern 125 may be a through hole that is formed in a portionof the first conductive pattern 120. The insulation pattern 125 has acircular shape when viewed from above with a diameter D. For example,the diameter D of the insulation pattern 125 may be about 50 μm to about200 μm. The diameter D of the insulation pattern 125 may otherwise varywithin the alignment error range.

The second insulation member 130 is disposed over the first insulationmember 110 and consequently covers the first conductive pattern 120. Thesecond insulation member 130 includes insulation material.

A via hole 132 passes through the second insulation member 130. In thepresent embodiment, when the first conductive pattern 120 is formedwithin the alignment error range, the via hole 132 is located at theportion corresponding to the insulation pattern 125 of the firstconductive pattern 120 (as shown in FIG. 2). When the first conductivepattern 120 is formed outside of the alignment error range, the via hole132 will be located at a portion of the first conductive pattern 120adjacent to the insulation pattern 125 (as shown in FIG. 3).

A conductive via 145 is placed inside the via hole 132 formed in thesecond insulation member 130. In the present embodiment, the conductivevia 145 may have a cylindrical shape. The conductive via 145 having acylindrical shape has a diameter D1 that is smaller than the diameter Dof the insulation pattern 125. In the present embodiment, the area ofthe insulation pattern 125 may be about 105 to 200% of the area of theconductive via 145.

The second conductive pattern 150 is disposed over the second insulationmember 130. In the present embodiment, the conductive via 145 and thesecond conductive pattern 150 may be formed integrally.

An examples of material that may be used as the conductive via 145 andthe second conductive pattern 150 include aluminum, aluminum alloy,copper, cooper alloy, and metal alloy, etc.

Hereinafter, the operation of the pattern alignment error detectingapparatus in accordance with the first embodiments of the presentinvention will be described with reference to the attached drawings.

FIG. 2 shows the case where the first conductive pattern 120 is disposedwithin the alignment error range. A plating solution may be applied tothe second conductive pattern 150. The conductive via 145 and the firstconductive pattern 120 are spaced apart from each other (i.e. they don'tconnect) and thus the DC voltage Vd applied to the first conductivepattern 120 does not reach the second conductive pattern 150 through theconductive via 145.

Therefore, when the first conductive pattern 120 is disposed within thealignment error range, the second conductive pattern 150 does notreceive DC voltage Vd, and consequently a plated layer is not formedover the second conductive pattern 150 even when the second conductivepattern 150 comes into contact with a plating solution. When the platingarea is not formed, the fact that the first conductive pattern 120 isdisposed within the alignment error range is confirmed. Alternatively,it is possible to confirm that the first conductive pattern 120 isdisposed within the alignment error range, by measuring the voltage ofthe second conductive pattern 150 rather than applying a platingsolution.

FIG. 3 is a cross-sectional view illustrating that the first conductivepattern shown in FIG. 2 is disposed out of the alignment error range.

FIG. 3 shows a case where the first conductive pattern 120 is disposedout of the alignment error range. In FIG. 3, the conductive via 145 iselectrically connected to the first conductive pattern 120. Therefore,the DC voltage Vd applied to the first conductive pattern 120 is reachesthe second conductive pattern 150 through the conductive via 145.

Therefore, when the plating solution is applied to the second conductivepattern 150 and the first conductive pattern 120 is out of the alignmenterror range, the second conductive pattern 150 receives DC voltage Vdand a plated layer 155 is formed over the second conductive pattern 150.Alternatively, it is possible to confirm easily that the disposition ofthe first conductive pattern 120 is out of the alignment error range bymeasuring the voltage of the second conductive pattern 150 rather thanapplying the plating solution.

FIG. 4 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a second embodiment of the presentinvention. FIG. 5 is a cross-sectional view taken along line II-II′ inFIG. 4 showing a case where the first conductive layer is formed withinthe alignment error range. FIG. 6 shows a case where the firstconductive layer is formed outside of the alignment error range.

Referring to FIGS. 4, 5, and 6, the pattern alignment error detectingapparatus 200 includes a first insulation member 210, a first conductivepattern 220 having an insulation pattern 225, a second insulation member230, and a second conductive pattern 250 having a conductive via 245.

The first conductive pattern 220 is disposed over the first insulationmember 210. The insulation member includes an insulation material. Thefirst conductive pattern 220 is electrically connected, for example, toa power line (not shown) through which a DC power source Vd is applied.

In the present embodiment, examples of material that may be used as thefirst conductive pattern 220 and the power line include aluminum,aluminum alloy, copper, cooper alloy, metal alloy, etc.

The first conductive pattern 220 includes the insulation pattern 225.The insulation pattern 225 may be disposed, for example, on the centerpart of the first conductive pattern 220.

In the present embodiment, the insulation pattern 225 may be disposedover the first conductive pattern 220. The insulation pattern 225 may bean insulation layer disposed over the first conductive pattern 220, oralternatively, the insulation pattern 225 may be a photoresist patterndisposed over the first conductive pattern 220.

The insulation pattern 225 disposed over the first conductive pattern220 has a disc shape with a diameter D when viewed from above. Thediameter D of the insulation pattern 225 may be about 50 μm to about 200μm. The diameter D of the insulation pattern 225 may otherwise varywithin an alignment error range.

The second insulation member 230 is disposed over the first insulationmember 210 and consequently covers the first conductive pattern 220. Thesecond insulation member 230 includes insulation material.

A via hole 232 is located in the second insulation member 230. The viahole 232 passes through the second insulation member 230. In the presentembodiment, when the first conductive pattern is formed within thealignment error range (as shown in FIG. 5), the via hole 232 is formedin the area of the second insulation layer that corresponds to theinsulation pattern 225 disposed over the first conductive pattern 220.When the first conductive pattern is formed outside of the alignmenterror range (as shown in FIG. 6), the via hole 232 is formed on aportion of the first conductive pattern 220 adjacent to the insulationpattern 225.

A conductive via 245 is placed inside the via hole 232 formed in thesecond insulation member 230. In the present embodiment, the conductivevia 245 may have a cylindrical shape. The conductive via 245 having acylindrical shape has a diameter D1 that is smaller than the diameter Dof the insulation pattern 225 disposed over the first conductive pattern220. In the present embodiment, the area of the insulation pattern 225may be about 105 to 200% of the area of the conductive via 245.

The second conductive pattern 250 is disposed over the second insulationmember 230. In the present embodiment, the conductive via 245 and thesecond conductive pattern 250 may be formed integrally.

Examples of material that may be used as the conductive via 245 and thesecond conductive pattern 250 include aluminum, aluminum alloy, copper,cooper alloy, metal alloy, etc.

Hereinafter, the operation of the pattern alignment error to detectingapparatus in accordance with the second embodiments of the presentinvention will be described with reference to the attached drawings.

FIG. 5 shows the case where the first conductive pattern 220 is disposedwithin the alignment error range. In the pattern alignment error device,a plating solution may be applied to the second conductive pattern. Whenthe first conductive pattern 220 is disposed within the alignment errorrange, the conductive via 245 is disposed over the insulation pattern225 of the first conductive pattern 220, and thus the DC voltage Vdapplied to the first conductive pattern 220 does not reach the secondconductive pattern 250 through the conductive via 245 due to theinsulation pattern 225.

Therefore, when the first conductive pattern 220 is disposed within analignment error range, the second conductive pattern 250 idoes notreceive the DC voltage Vd and consequently a plated layer does not formover the second conductive pattern 250 even when the second conductivepattern 250 comes into contact with a plating solution. When the platingarea is not formed, the fact that the first conductive pattern 120 isdisposed within the alignment error range is confirmed. Alternatively,it is possible to confirm that the first conductive pattern 220 isdisposed within the alignment error range by measuring the voltage ofthe second conductive pattern 250 rather than applying a platingsolution.

FIG. 6 is a cross-sectional view illustrating that the first toconductive pattern shown in FIG. 5 is disposed out of the alignmenterror range.

FIG. 6 shows a case where the first conductive pattern 220 is disposedout of the alignment error range. The conductive via 245 is electricallyconnected to the first conductive pattern 220. Therefore, the DC voltageVd applied to the first conductive pattern reaches the second conductivepattern 250 through the conductive via 245.

Therefore, when the plating solution is applied to the second conductivepattern and the the first conductive pattern 220 is out of the alignmenterror range, the second conductive pattern 250 receives DC voltage Vdand thus a plated layer 255 is formed over the second conductive pattern250. Alternatively, it is possible to confirm easily that thedisposition of the first conductive pattern 220 is out of the alignmenterror range by measuring the voltage of the second conductive pattern250 rather than applying the plating solution.

FIG. 7 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a third embodiment of the presentinvention. FIG. 8 is a cross-sectional view taken along line III-III′ inFIG. 7 showing a case where the first conductive layer is formed withinthe alignment error range. FIG. 9 shows a case where the firstconductive layer is formed outside of the alignment error range.

Referring to FIGS. 7, 8, and 9, the pattern alignment error detectingapparatus 300 includes a first insulation member 310, a first conductivepattern 320 having an insulation pattern 325, a second to insulationmember 330, a second conductive pattern 350 having a conductive via 345,and a third conductive pattern 370 having an additional conductive via365.

The first conductive pattern 320 is disposed over the first insulationmember 310. The first insulation member 310 includes insulationmaterial.

The first conductive pattern 320 includes the insulation pattern 325.The insulation pattern 325 may be disposed, for example, at a centerpart of the first conductive pattern 320. In the present embodiment, theinsulation pattern 325 may be a through hole that is formed in a portionof the first conductive pattern 320. The insulation pattern 325 has acircular shape with a diameter D when view from above. The diameter D ofthe insulation pattern 325 may be about 50 μm to 200 μm. The diameter Dof the insulation pattern 125 may otherwise vary within the alignmenterror range. Alternatively, the insulation pattern may instead be aninsulation layer or a photoresist pattern disposed over the firstconductive pattern 320.

The second insulation member 330 is disposed over the first insulationmember 310 and consequently covers the first conductive pattern 320. Thesecond insulation member 330 includes insulation material.

A via hole 332 passes through the second insulation member 330. In thepresent embodiment, when the first conductive pattern 320 is formedwithin the alignment error range, the via hole 332 is formed at aportion corresponding to the insulation pattern 325 of the firstconductive pattern 320. When the first conductive pattern 320 is formedoutside of the alignment error range, the via hole 332 will be formed ata portion of the first conductive pattern 320 adjacent to the insulationpattern 325 (as shown in FIG. 9).

A conductive via 345 is placed inside the via hole 332 formed in thesecond insulation member 330. In the present embodiment, the conductivevia 345 may have a cylindrical shape. The conductive via 345 having acylindrical shape has a diameter D1 that is smaller than the diameter Dof the insulation pattern 325. In the present embodiment, the area ofthe insulation pattern 325 may be about 105 to 200% of the area of theconductive via 345.

The second conductive pattern 350 is disposed over the second insulationmember 330. In the present embodiment, the conductive via 345 and thesecond conductive pattern 350 may be formed integrally.

An examples of material that may be used as the conductive via 345 andthe second conductive pattern 350 include aluminum, aluminum alloy,copper, cooper alloy, and metal alloy, etc.

The second insulation member 330 includes an additional via hole 363that passes through the second insulation member 330. In the presentembodiment, the additional via hole 363 is disposed at a portion of thefirst conductive pattern 320 adjacent to the insulation pattern 325. Theadditional conductive via 363 is placed inside the additional via hole363, and the conductive via 363 contacts the first conductive pattern320.

The third conductive pattern 370 is disposed over the second insulationmember 330. In the present embodiment, the third conductive pattern 370and the additional conductive via 365 may be formed integrally. Thethird conductive pattern 370 is electrically connected to a power line380 that provides a DC voltage Vd to the third conductive pattern 370.

Hereinafter, the operation of the pattern alignment error detectingapparatus in accordance with the third embodiments of the presentinvention will be described with reference to the attached drawings.

FIG. 8 shows the case where the first conductive pattern 320 is disposedwithin the alignment error range. A plating solution may be applied tothe second conductive pattern 350 and the third conductive pattern 375.The third conductive pattern 370 is electrically connected to the firstconductive pattern 320 by the additional conductive via 365. However,the conductive via 345 is spaced apart from the first conductive pattern120. Therefore, the DC voltage Vd applied to the third conductivepattern 370 by the power line 380, which in turn flows through theadditional conductive via 365 and the first conductive pattern 320 ,does not reach the second conductive pattern 350 through the conductivevia 345.

Therefore, when the first conductive pattern 320 is disposed within thealignment error range, the second conductive pattern 350 does notreceive the DC voltage Vd, and consequently a plated layer is not formedover the second conductive pattern 350 even when the second conductivepattern 350 comes into contact with a plating solution. When the platingarea is not formed, the fact that the first conductive pattern 120 isdisposed within the alignment error range is confirmed.

Alternatively, it is possible to confirm that the first conductivepattern 320 is disposed within the alignment error range by measuringthe voltage of the second conductive pattern 150, rather than applying aplating solution. When the plating solution is applied to the second andthird conductive patterns 350 and 370, although a plated layer will notform over the second conductive pattern when the first conductivepattern is disposed within the alignment error range, a plated layer 375will form over the third conductive pattern 370.

FIG. 9 is a cross-sectional view illustrating that the first conductivepattern shown in FIG. 8 is disposed out of the alignment error range.

FIG. 9 shows a case where the first conductive pattern 320 is disposedout of the alignment error range. In FIG. 9, the conductive via 345 iselectrically connected to the first conductive pattern 320.

Therefore, the DC voltage Vd applied to the third conductive pattern 370by the power line 380, which then travels through the additionalconductive via 365 and the first conductive pattern, reaches the secondconductive pattern 350 through the conductive via 345.

Therefore, when the plating solution is applied to the second conductivepattern, and the first conductive pattern 320 is out of the alignmenterror range, the second conductive pattern 350 received DC voltage Vdand a plated layer 355 is formed over the second conductive pattern 350.Alternatively, it is possible to confirm easily that the the firstconductive pattern 320 is out of the alignment error range by measuringa voltage applied to the second conductive pattern 350 rather thanapplying the plating solution.

FIG. 10 is a plan view illustrating an apparatus for detecting patternalignment error in accordance with a fourth embodiment of the presentinvention. FIG. 11 is a cross-sectional view taken along line IV-IV′ inFIG. 9 showing a case where the first conductive layer is formed withinthe alignment error range. FIG. 3 shows a case where the firstconductive layer is formed outside of the alignment error range.

Referring to FIGS. 10, 11, and 12, the pattern alignment error detectingapparatus 400 includes a first insulation member 410, a first conductivepattern 420 having a plurality of insulation patterns 424, a secondinsulation member 430, and a second conductive pattern 450 having aplurality of conductive vias 464.

The first conductive pattern 420 is disposed over the first insulationmember 410. The first insulation member 410 includes insulationmaterial. The first conductive pattern 420 is electrically connected,for example, to a power line (not shown) through which a DC power sourceVd is applied.

In the present embodiment, an example of materials that may be used asthe first conductive pattern 420 and the power line include aluminum,aluminum alloy, copper, cooper alloy, metal alloy, etc.

The first conductive pattern 420 includes the insulation patterns 424.In the present embodiment, the insulation patterns 424 may be, forexample, through holes that are formed in the first conductive pattern420. The insulation pattern 125 has a circular shape when view fromabove. For example, the diameter of each insulation pattern 424 may be50 μm to 200 μm. The diameter of the insulation pattern 424 mayotherwise vary within the alignment error range.

The insulation patterns 424 are disposed along the Y-axis shown in FIG.10. In the present embodiment, the number of the insulation patterns 424is five. Hereinafter, the five insulation patterns are referred to as afirst insulation pattern 425, a second insulation pattern 426, a thirdinsulation pattern 427, a fourth insulation pattern 428, and a fifthinsulation pattern 429.

In the present embodiment, the first to fifth insulation patterns 425 to429 each have different sizes. For example, the first insulation pattern425 has a first size, the second insulation pattern 426 has a secondsize, the third insulation pattern 427 has a third size, the fourthinsulation pattern 428 has a fourth size, and the fifth insulationpattern 429 has a fifth size.

The second insulation member 430 is disposed over the first insulationmember 410 and consequently covers the first conductive pattern 420. Thesecond insulation member 430 includes insulation material.

The second insulation member 430 includes a plurality of via holes 435that each pass through the second insulation member 430. In the presentembodiment, when the first conductive pattern 420 is formed within thealignment error range, the via holes 435 are formed at portions of thesecond insulation member corresponding to the respective insulationpatterns 425 to 429. When the first conductive pattern 420 is formedoutside of the alignment error range, the via holes 435 may be formed atportions of the first conductive pattern 420 adjacent to the insulationpatterns 425 to 429.

The conductive vias 465, 466, 467, 468 and 469 are placed respectivelyinside the via holes 435 formed in the second insulation member 430. Inthe present embodiment, the conductive vias 465 to 469 may have, forexample, a cylindrical shape.

The conductive vias 465 to 469 having the cylindrical shape have thesame diameters. The diameter of the conductive vias 465 to 469 issmaller than the diameter of the insulation patterns 425 to 429. In thepresent embodiment, areas of the insulation patterns 425 to 429 may be105 to 200% of the areas of the conductive vias 465 to 469 respectively.

The second conductive patterns 451, 452, 453, 454, 455 are disposed overthe second insulation member 430. In the present embodiment, theconductive patterns 450 are formed integrally with the correspondingconductive via 465 to 469.

Hereinafter, the operation of the pattern alignment error detectingapparatus in accordance with the fourth embodiments of the presentinvention will be described with reference to the attached drawings.

FIG. 11 shows the case where the first conductive pattern 420 isdisposed within an alignment error range. A plating solution may beapplied to the second conductive patterns 450. The conductive vias 145and the first conductive pattern 420 are spaced apart from each other(i.e. they don't connect) and thus the DC voltage Vd applied to thefirst conductive pattern 420 does not reach the second conductivepatterns 450 through the conductive vias 465 to 469.

Therefore, when the first conductive pattern 420 is disposed within thealignment error range, the second conductive pattern 450 does notreceive DC voltage Vd and consequently a plated layer is not formed overeach second conductive pattern 450 even when the second conductivepattern 450 comes into contact with a plating solution. When the platingarea is not formed, the fact that the first conductive pattern 420 isdisposed within the alignment error range is confirmed. Alternatively,it is possible to confirm that the first conductive pattern 420 isdisposed within the alignment error range by measuring the voltage ofeach second conductive pattern 450, rather than applying the platingsolution.

FIG. 12 is a cross-sectional view illustrating that a first conductivepattern shown in FIG. 11 is disposed out of an alignment error range.

FIG. 12 shows a case where the first conductive pattern 420 is disposedout of the alignment error range. When the first conductive pattern 420is disposed out of the alignment error range, some of the conductivevias 465 to 469 may be electrically connected to the first conductivepattern 420. For example, the conductive via 469 corresponding to thefifth insulation pattern 429 has a relatively small area, and thus iselectrically connected to the first conductive pattern 420.

Therefore, when the plating solution is applied to the second conductivepatterns 450, and the DC voltage Vd applied to the first conductivepattern 420 reaches the second conductive pattern 455 through theconductive via 469, a plated layer 480 is formed over the secondconductive pattern 455. Alternatively, it is possible to confirm easilythat the disposition of the first conductive pattern 420 is out of thealignment error range by measuring a voltage applied to the secondconductive patterns 451 to 455 rather than applying the platingsolution.

In a case where the alignment error range of the first conductivepattern 420 is small, the number of the second conductive patterns 451to 455 on which the plated layer is formed is small. In contrast, in acase that the alignment error range of the first conductive pattern 420is large, the number of the second conductive patterns 451 to 455 onwhich the plated layer is formed increases.

The pattern alignment error detecting apparatus described above can beapplied to various devices having multi-layered wiring. For example, thepattern alignment error detecting apparatus may be applied to a printedcircuit board having multi-layered wiring, a semiconductor chip havingmulti-layered wiring, a semiconductor package having multi-layeredwiring, etc.

As is apparent from the above description, there is a major advantage inusing the present invention, in that the alignment error of the lowerwiring of a multi-layered wiring can be easily recognized.

Although specific embodiments of the present invention have beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and the spirit of theinvention as disclosed in the accompanying claims.

1. A method for a detecting whether or not a pattern alignment error exists in a printed circuit board having an apparatus comprising: a first conductive pattern disposed over a first insulation member; a second insulation member covering the first conductive pattern; a second conductive pattern disposed on the second insulation layer; a conductive via electrically connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern, the method comprising: applying a power source to the first conductive pattern; contacting a plating solution over the second conductive pattern; and inspecting the second conductive pattern for a plated layer grown on top of second conductive pattern to detect whether or not the pattern alignment error exists.
 2. The method of claim 1, wherein when the plated layer is found on top of the second conductive pattern then the pattern alignment error is determined to exist.
 3. The method of claim 1, wherein when the plated layer is not found on top of the second conductive pattern then the pattern alignment error does is determined not to exist. 